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Risc-V support in SlapOS

Describes the support of RISC-V architecture in SlapOS
  • Last Update:2024-06-26
  • Version:001
  • Language:en

RISC-V is an open standard ISA and SlapOS is adding support to run fully on it.

This pages describes what we already achieved and what we plan to do.


We can find more and more machines with RIC-V CPUs (servers, laptops, ...). The SoC with RISC-V are trendy (see the SG2380 from MilkV for example) because the architecture is open and there are a lot of open implementation of this architecture.

In the office we bought a https://milkv.io/pioneer board with the following spec:

  • CPU: SOPHGO SG2042 Chip (64-core C920, RVV 0.71) 
    • Main Frequency: 2GHz
    • L1 Cache: I:64KB and D:64KB
    • L2 Cache: 1MB/Cluster
    • L3 Cache: 64MB System Cache
    • Typical power consumption: 120W
    • DDR: 4 channel 3200Hz ECC RDIMM/UDIMM/SODIMM
    • PCI-E: 2 x 16x Gen4 with CCIX support
  • RAM: 128GB 3200MHz DDR4
  • Graphical card: AMD R5 230
  • Network Card: Intel X540-T2
  • Disk: 1TB PCIe 3.0 SSD
  • PSU: MSI A350 350W



Many standard Linux distribution are adding support for RISC-V architecture. This is the case at least for Debian and Fedora.

For now we are using Fedora 40.


Current support in SlapOS

The first goal was to be able to run SlapOS on the RISC-V architecture. This needed a few adaptations in the way we are compiling our software. Mainly we added support for newer CPU architectures.

We managed to compile a slapos-node package for Fedora 40 on 2024, May the 22nd.

Then we wanted to run a full testsuite on this architecture in order to evaluate the amount of work for full support. In order to do this, we needed to compile our testsuite software. This again needed some adaptations of our code.


The future

With the run of our full testsuite, we realized that we still have many work to do to support fully the RISC-V architecture. But thanks to SlapOS agility, for sure, we will manage to support fully the RISC-V architecture.

When support will be complete, we can easily envision our ORS product with a RISC-V CPU inside. This will increase again the openness of our product.